micro:bit Circuit Schematics, assembly and test point map
- V2 pinmap
- Key Features
- Assembly Diagram
- Test point map
- Further information
This page discusses the micro:bit schematic and Bill of Materials BOM, which shows the electrical connections of the micro:bit and the components used in it.
The micro:bit V1.3 and V1.5 schematic is available from the BBC’s micro:bit hardware repository.
The micro:bit V2 schematic is available from the Micro:bit Educational Foundation microbit-v2-hardware repository.
If you’re looking to make something of your own based on the micro:bit, you might prefer to use our ‘Reference Design’ which is based on a radio module and has space on the layout for you to add your own components.
Below is the pinmap and allocation of the nRF52833, more information is available on the micro:bit V2 schematic
|GPIO on nRF52833||Allocation||KL27 Landing||Edge Connector name|
Below, we’ve extracted some useful details about the hardware that anyone implementing software for the micro:bit, interfacing to it, or designing an add-on board for it should find useful.
The LED matrix is physically laid out as a 5x5. On the V2 board this is implemented as a 5x5 matrix, but in the V1, this is implemented as a scanned matrix of 9x3 (i.e. 9 columns by 3 rows). Row 2 Col 8, and Row 2 Col 9 are not used.
The LED matrix is driven via a high-speed multiplex generated by application processor software. This software also uses the LED Row and Col pins to implement the light sensing feature, as such you may see a difference in sensitivity between board revisions. Some of the Columns appear on the edge connector, so if you want to use extra GPIO pins, you have to disable the display in software.
The Interface sheet shows the KL26V1/KL27V2 processor, which is an NXP microcontroller with an Arm processor, that implements the USB protocol for the USB connector. This provides a method for loading code onto the application processor, using a drag and drop interface.
The USB protocol handler on this processor implements a Mass Storage Class device in order to offer the drag and drop code load interface. It also provides a Connected Device Class that allows a serial port interface to be used across the USB.
The interface processor also contains an on-board regulator that steps down the USB voltage to 3.3V suitable for powering the rest of the micro:bit, and you can draw 120mAV1/300mAV2 from this processor regulator. A TVS device is fitted to suppress ESD spikes and out of range voltages that could be present on the USB connector.
This processor does not have any connection to the GPIO pins on the micro:bit.
There is one combined motion sensor IC on the micro:bit, that contains an accelerometer and a magnetometer. The accelerometer measures acceleration in 3 axes, and the magnetometer can be used as a compass, as well as a magnetic field detector.
In V2 there is a combined open drain, active low, interrupt signal (
COMBINED_SENSOR_INT) to the application processor for the motion sensors and the KL27. Any device can asset this signal and the application processor has to query the individual devices to locate the origin.
The magnetometer can generate one processor interrupt for the application processor, and the accelerometer can generate two different processor interrupts in V1 or just one in V2.
Note, the physical orientation of this IC is important for binary compatibility with the driver code in the application processor, which assumes a particular physical orientation in its calculations.
Power to the micro:bit can be provided by 3 sources: The USB, the battery connector, and the 3V pad on the edge connector.
For USB powering, the KL26 interface processor has an on-board regulator that brings the external USB voltage into the correct range for the micro:bit board.
A low-Vf diode (in this case about 0.23V max) is used to switch between sources. The diode prevents back-powering of any source from any other source.
Care should be taken if powering the micro:bit from the 3V pad on the edge connector, as the trace from that pad is connected directly to the ICs on the board. Please check the datasheets for the appropriate ICs for their maximum tolerable voltages.
The main application processor runs both the runtime code and user code, as a single binary image.
Code is loaded into this processor via the interface processor.
Communications via USB serial is done via the interface processor.
All GPIO pins on the edge connector are serviced by this application processor.
All bluetooth features are provided by a SoftDevice stack loaded into this processor.
The nRF52V2 features additional NFC functionality on P0.09(NFC1) and P0.10(NFC2) that is disabled by default, but can be configured using the nRF5SDK.
The edge connector is the main interface to external components attached to the micro:bit.
This interface has a range of digital, analog, touch, PWM, and serial communications interfaces.
10Mohm weak pull-up resistors are fitted on P0 P1 P2 and logoV2 for use in touch sensing mode, where they provide a weak pull-up to the supply providing a default high input and the user touching the GND pad pulls the pin down towards 0V, providing a low input. When in non touch modes, these pads have stronger internal pull-downs enabled in the software, so that the default input state when not connected is ‘low’.
Guard pins are provided both sides of the 3V and GND pads, so that shorting by crocodile clips does not degrade the features of the device by causing spurious inputs.
Both the front and the back of each of the 5 round ring pads are electrically connected.
A number of pins have alternate assigned functions for use by the micro:bit, many of these can be disabled in software to gain more general purpose IO pins.
The V2 board revision has a notched edge connector to make it easier to connect crocodile clips and wire etc. This does not affect compatibility with peripherals with edge connector sockets.
The specific dimensions of the board are:
- 51.60mm(w) 42.00mm(h) 11.65mm(d)
- JST connector to board 5.50mm
- button depth to board 4.55mm
- V2 speaker depth to board 3.00mm
The following image of the V2 revision is taken from the micro:bit V2 assembly diagram provided by Avid.
Test point map
The rear view of the device has been adapted to highlight the test points and describe their purpose.
Exposed Test Points
|TP1||U5 Bootmode - used to enter the ROM bootloader on the KL27Z|
|TP17||Access to Pin 1 on Battery connector|
|TP19||Access to VBUS line on USB Connector|
|TP20||Access for debugging internal I2C bus - SCL|
|TP21||Access for debugging internal I2C bus - SCL|
|TP9||VREG - Actually the power rounded rectangular pad|
|TP10||GND - Actually the GND rounded rectangular pad|
Covered test points (Solder mask to be removed to access test point)
|TP11||U2_SWDCLK - used to debug nRF52833|
|TP12||U2_SWDIO - used to debug nRF52833|
|TP4||U5_SWD_DIO - used for debugging KL27Z|
|TP3||U5_SWD_TCLK - used for debugging KL27Z|
|TP2||U5_IF_NRST - used for debugging KL27Z|
|TP5||VREG - additional VREG, this is connected to TP9|